In a large scale VLSI circuit design project, an initial step is to create a description of chip functionality. This description is created in Register Transfer Language (“RTL”). One of the considerations in a circuit design is to optimize the resistance capacitance (RC) values of the configuration, while minimizing the negative effects that the RC values may have on timing. Connection paths for signals between different components of a VLSI circuit have inherent RC values that may cause delays in propagation. These values are referred to herein as RC interconnect parasitics.
According to known design techniques, RC parasitic values have been either ignored completely or approximated by considering only a capacitance component at the initial design stage of a VLSI design project. This was acceptable because RC parasitic delays were typically low compared with gate delays. According to this method, the resistive component was disregarded at the initial layout stage, with the total line capacitance being lumped together. In the past, this produced a fair estimation.
Another design method is to manually place RC values representative of the RC interconnect parasitics into the schematics. This involves roughly planning out where various blocks are to be placed, then manually measuring or estimating the length of a wire of interest based on a drawn floorplan of the design. In this way, resistance and capacitance parasitics may be manually annotated onto the schematic. The schematic with the estimated interconnect and via parasitic elements would then be analyzed through timing tools for timing and area optimization. This process requires significant manual effort on the part of the designer in measuring and estimating the wire lengths between circuit components in the design, and then annotating the schematic with these parasitic electrical elements. The accuracy and completeness of the estimated wire lengths between circuit components depends on the experience of the designer, and can vary significantly within a large VLSI circuit design team. Using this approach, the timing of the design will not be known with a high degree of confidence until the layout is completely routed and extracted timing is performed. This manually intensive process further makes it difficult to consider the RC parasitic values as components are moved or different configurations are explored, since the parasitic values would need to be recalculated. Another drawback to this design method is that the design effort is relatively far along before RC parasitic delays are considered, making it difficult to revise a design to overcome a negative impact of such RC parasitic delays. The present invention provides techniques for addressing these drawbacks of the prior approaches.